Signals are transmitted between LSI chips, between a plurality of circuit blocks within a casing, and between casings. A data signal transmission rate is demanded to be increased.
The performance of components configuring a computer and other information processing devices has improved considerably. For example, performances of a memory, a processor, and a switch LSI have improved. In order to improve the performance of a system, it is necessary to improve the signal transmission rate between these components or elements as well as improving the performance of the components. For example, in order to improve the performance of a computer (server), it is effective to improve the signal transmission rate between a memory, such as an SRAM and a DRAM, and a processor. In addition to a server, it is effective to improve the data rate in signal transmission and reception inside and outside a device as the performance of an information processing device, such as a communication infrastructure-specific device is improved.
In a communication system having improved the data rate, after converting parallel data into serial data, the transmission side outputs the data to a transmission line as one-bit data in accordance with a transmission clock. The reception side recovers a reception clock corresponding to the transmission clock from the received data and takes in data at optimum timing. Because of this, the reception side has a circuit configured to perform clock data recovery (CDR) to recover the reception clock from the received data and a phase shifter configured to adjust the phase of the clock. A circuit that performs CDR is referred to as a CRU (Clock Recovery Unit). The CRU and the phase shifter are circuits whose circuit scale is large.
Further, in high-rate data communication, it is important to receive data in a stable manner and on the reception side, deterioration of received data signal is measured. The quality of the received data signal on the reception side is normally represented by an eye-opening, and therefore, an eye-opening monitoring function to perform eye-opening measurement is provided on the reception side and the eye-opening measurement is performed at the time of initialization and whenever necessary.
As described above, an attempt is made to improve the data rate in serial communication, however, it is difficult to improve the data rate greatly. Because of this, a communication system has been examined, which improves the data communication rate by providing a plurality of lanes through which communication is performed at a data rate resembling the above-mentioned data rate and by performing parallel data communication. In this communication system, the communication rate, which is the data rate of each lane multiplied by the number of lanes, is obtained, and therefore, the communication rate improves greatly.
This communication system has a communication path having a plurality of transmission lines (lanes), a transmitter having a plurality of transmission circuits, and a receiver having a plurality of reception circuits. As to the clock of the communication system, there are two cases: a case where clock sources having similar oscillation frequencies are provided in the transmitter and the receiver, respectively; and a case where a clock transmission line is provided separately from that of data, and a clock is transmitted from the transmitter and the receiver recovers the received clock. In either case, when the clock rate is high, a deviation of phase between lanes cannot be ignored, and therefore, the CRU is provided in each of the plurality of reception circuits. In the following explanation, a communication system is explained as an example, in which clock sources having similar oscillation frequencies are provided in the transmitter and the receiver, respectively.
Further, the communication system having a plurality of lanes is also required to measure the quality of the received data signal in each of the plurality of reception circuits in the case where the communication rate of each lane is high, and therefore, the eye-opening monitoring function is provided in each of the plurality of reception circuits. However, in order to implement the eye-opening monitoring function, it is necessary to separately provide an eye-opening monitoring circuit resembling the CRU for implementing the CDR function or a phase shifter of the CRU. If the CRU and the circuit having implemented the eye-opening monitoring function are provided in each of the plurality of reception circuits, there is such a problem that the circuit (hardware) scale increases.